Binary signal voltage level standardizer



y 1968 T. E. GILLIGAN 3,384,765

BINARY SIGNAL VOLTAGE LEVEL STANDARDIZER Original Filed Aug. 19, 1963 5Sheets-Sheet l- EMITTER FOLLOWER W QAL -VA VB BINARY SIGNAL VOLTAGE ISTANDARDIZER I j I EOUT E I EOUT I IN m Fig/ WEAK/1" 1 I I I I IRIJIIDLE AND BINARY INPUT I I BINARY INPUT I i ONLY C\\ NOINPUT/ I I I I I IIVALLEY/ I- D I I I I I I 2-I0 2-20 2-50 I I v J 0 m ETI+ E I I mGRAPHICAL ANALYSIS OF BISTABLE INVERTER CIRCUIT INVENTOR.

THOMAS E. GILLIGAN Fig. 2

y 1968 T. E. GlLLlGAN 3,384,765

BINARY SIGNAL VOLTAGE LEVEL STANDARDIZER Original Filed Aug. 19, 1963 5Sheets-Sheet LOAD LINE 1 Veb QES-IZ ASSUME R =R x||L1||| \|1a| l I {Him: g 0 Z 2 INVENTOR lOhS/DIV THOMAS EGILLIGAN NEGATIVE GOING INPUTSIGNAL I 7 May 21, 1968* i :I ILLIEAN 3,384,765

E VOLTS BINARY SIGNAL VOLTAGE LEVEL STANDARDIZER Original Filed Aug. 19,1963 I 5 Sheets-Sheet s IOns/DIV POSITIVE some OUTPUT SIGNAL +3 z; 2 ffIOI1S/ DIV POSITIVE GOING INPUT SIGNAL ii +I I E VOLTS Ions/DIV I THOMASILIAN NEGATIVE some OUTPUT SIGNAL EG LG INVENTOR May 21, 1968 T. E.GILLIGAN 3,384,765

I BINARY SIGNAL VOLTAGE LEVEL STANDARDIZER TIME Original Filed Aug. 19,1963 5 Sheets-Sheet 4 Fig.6B E ITURNQI II I OI ITURN OI I DEF I OFF Em I6-52 I 6-62: I T I I I I l a 654 E |656I rea 1 g Y v I I z: E0|FF l I II H f l ON I ON ON I 2 I l I I l I I Fig 6A I; I 1 5 I I l BIAS CLOCKEouT QIOIN i OIOEF IDION? I I I I L to u t2 ts t4t5 ts t1 ts t9DIEFERENTIATOR FIXED NEGATIVE BIAS WITH INPUT AND OUTPUT VOLTAGE BOTHLOW FIXED NEGATIVE BIAS WITH INPUT AND OUTPUT VOLTAGE BOTH HIGH Fig. 7A

..I Cp 0 m B v I OUIESGENT FLIP- FLOP EXTREMES C NEGATIVE CLOCK'BIAS ANDLOW OUTPUT VOLTAGE D LOW} INPUT 1 HIGH VOLTAGES .F 7B

POSITIVE GLOGK BIAS AND INVENTOR. |NPUT HIGH OUTPUT VOLTAGE THOMASEG|LL|GAN VOLTAGES HIGH CLOCK TRIGGERED FLIP-FLOPEIITREMEG y 21, 1968 IT. E. GILLIGAN 3,384,765

BINARY SIGNAL VOLTAGE LEVEL STANDARDIZER Original Filed Aug. 19, 1963 V5 Sheets-Sheet 5 LOADS n u I ll I AND GATE I I5V TRANSISTOR OR I5V I IGATE I I I 5 m R2 i 1 R2 0 I I 2 012 I l 5Ix 5 I 1 I RI I I I I RI RI RII Q 1 I I i I -|5 I I L fl YI l I :"AND" GATE 2 R2 I R2 I o I an I M. I020 l 1 O I i I I RI O I 02X 1 I g I I I RI iRI RI E 02 1 5V 1 I I I I II5V I I I I I I AND GATE N II I I QJKIERZ I I I :3 I I I I m 2m I I I II I I INVENTOR THOMAS E. GILLIGAN United States Patent Ofice 3,384,765Patented May 21, 1968 3,384,765 BINARY SIGNAL VOLTAGE LEVEL STANDARDIZERThomas E. Gilligan, Havertown, Pa., assignor to Burroughs Corporation,Detroit, Mich., a corporation of Michigan Continuation of applicationSer. No. 303,029, Aug. 19, 1963. This application July 25, 1966, Ser.No. 567,683 3 Claims. (Cl. 307268) This application is a continuation ofapplication S.N. 303,029 filed Aug. 19, 1963, and now abandoned.

This invention relates to the restandardizing or restoration of signalvoltage levels. It is particularly concerned with the standardizing orrestoring of binary voltage signal levels in a data-processing system.

In the field of data processing, especially in that portion of the fieldassociated with digital computers, one of the prime concerns of thesystem designer is the maintenance of a fixed pair of signal levelswhich are to be considered as the binary signal voltage values.Variation of these binary levels could, of course, be considerablytroublesome throughout the system unless some means were inserted to actas a reference for these binary values.

In any intricate binary electronic system where numerous strings ofrepetitive circuits are utilized, a problem which causes much diflicultyis deterioration of binary voltage signal levels. While this problem ispresent in analog signal systems, the signal continuity associatedtherewith considerably reduces the seriousness of the trouble. It is inthe digital system, where the information being relayed throughout thelogical organization is in the form of two discrete levels, that itspresence is most felt.

One of the prior solutions to the problem has been to use signal voltagelevels which were the same as the power source levels. This was usuallyaccomplished through the use of a saturated circuit condition for onediscrete binary level and a circuit cutoff condition for the other. Thissolution, however, was not entirely satisfactory. One of the problemswas the loss of operational speed by the circuits so operated. This lossis caused by the well-known time delays associated with transistorturn-on, turn-oil and storage times. These inherent losses are at theirpeak in a bistable circuit operated between cutoff and saturation.

Recently in computer design there has been a quest for higher circuitoperational speeds. This has been brought about mainly by the discoveryof new electronic components whose speed has far exceeded theoperational speeds realized in the circuits into which these componentshave been utilized. As a result of these improvements, much effort hasgone into methods of realizing the improved component speed by circuitmodifications which could approach the speed of the components. It waswell known that operation of such circuits in their middle or activeregion was most desirable from the viewpoint of operational switchingspeed. However, the failure to provide a means to standardize a firstand second voltage level within the middle region remained a barrier. Afurther impediment was the inability to restandardize and therebymaintain these levels throughout numerous circuit paths of the system.

A particular component which has had a significant impact on theimprovement of circuit speed is the tunnel diode. This is a device whichpossesses a negative resistance in a portion of its characteristiccurve. That is, for a partween two sections of positive resistance inthe diode current/ voltage characteristic. In these positive resistancesections an increase in voltage through a device will result in acorresponding increase in the current. An important circuit applicationof the tunnel diode has been its use as a bistable device. This isachieved by designing the circuit with a load line passing through bothpositive resistance sections of the current/voltage characteristic ofthe diode. The bistable configuration is operated by in creasing thevoltage across the diode in its initial positive resistance section toachieve a corresponding increase in current. This continues until acritical peak current is exceeded. At this critical time there is asudden shift from one positive resistance section to the other. Inswitching to this second positive region of the characteristic curve,the tunnel diode passes through its negative resistance region at anexceedingly high rate of speed. The switching rate is said to occur atthe speed of light. This characteristic is utilized by the presentinvention to achieve the improved transistor switching speed.

The present invention utilizes the bistable characteristic of the tunneldiode in a unique manner. It is known that it is possible to switch abinary signal transistor circuit between its alternate levels at a speedwhich approaches the switching speed of the tunnel diode. This wasaccomplished by connecting the tunnel diode in its bistable operatingmode to act as a switch across the input of a binary signal operatedtransistor circuit. However, in order to accomplish the return switchingof the tunnel diode to its initial state required the use of either abipolar input signal or some alternate resetting means. Thus, after thediode had been switched to its second state wherein the voltage dropacross the diode was in its high state, it was necessary to reduce thevoltage input signal to below its lower value in order to return thediode to its initial low voltage state. In the present invention theswitching may be accomplished without such reduction of the input signalbelow its lower voltage state. Further, most former tunnel diodeswitched transistor bistable circuits merely used the switch to activatethe transistor circuit between the usual binary levels of transistorcutoff and saturation, thereby retaining the speed disadvantagesassociated with such conditions. This is not so in the presentconfiguration. As mentioned, it is well known that a transistor circuitwhich is operated continuously in its active region responds much morerapidly to signal variations than does a transistor circuit that is ineither its cutoff or its saturated state. For example, before atransistor reaches saturated conduction, a certain amount of turn ontime is consumed. Conversely, after a transistor had been driven intoits saturated condition there is an inherent storage time which must beadded to the turn-01f time of the transistor circuit. This inherentadditional time is the time necessary for the transistor to come out ofits saturated condition. In the present invention, the storage time isnever imposed and both the turn-off and the turn-on time are reduced bycontinuous operation of the transistor in its active region. Formerschemes were unable to operate in this manner since the binary signallevels could not be standardized.

Further, the restandardizing of such binary levels after deteriorationthrough a string of logical circuits was a problem and the presentcircuit is used repetitively throughout the system to restandardize thesignal levels.

The present invention has still another advantage in that it enables theuse of logical circuitry which heretofore could not be utilized.

Most prior logical circuits including input gates in which conventionaldiodes were used have such diodes connected in a manner which requiresthe input binary signal to overcome a certain amount of back bias before3 such gates can be operated. This is necessary to reduce thesusceptability of the circuits to activation by spurious or noisesignals.

Thus, a. certain amount of time delay is purposely imposed at eachgating junction throughout the computer to reduce the possibility oferroneous activation of said circuits.

The present circuit, itself, possesses a high degree of noise immunity.This allows the use of diode gates which are activated entirely by theinput signal without the necessity of overcoming a back bias voltage.This noise immunity is achieved by the imposition upon the presentcircuit of a quality, probably best described as a hysteresis effect.

It is therefore the primary object of this invention to provide acircuit possessing the ability to create a standard set of binaryvoltage levels.

It is also an object of this invention to provide a circuit capable ofrestandardizing these binary signal levels throughout a digital system.

It is a further object of this invention to provide digital computercircuitry capable of satisfactory system performance which is operativein its region of highest switching speed, that is, operative in itsactive region.

It is a still further object of this invention to provide arestandardizing circuit having improved high speed switchingcharacteristics.

It is still a further object of this invention to provide a binaryvoltage level restandardizing level which reduces error accumulation byaccomplishing its standardizing action through inversion.

It is also an object of this invention to provide a restandardizingcircuit wherein the speed of the transistor switching operation issubstantially independent of the binary input signal.

It is also an object of this invention to provide a binary signalstandardizing circuit possessing a high degree of immunity to erroneousswitching activation in either direction by spurious or noise signalvoltages.

It is also an object of this invention to provide a binary signalstandardizing circuit which is entirely operative by said binary signalwithout need for additional resetting or clock signals to return thecircuit to its initial state.

It is still a further object of the present invention to provide a basicgate circuit of the diode AND transistor OR configuration wherein the ORgating is performed with a common node which is activated without theusual need for overcoming a back bias associated with a diodeconfiguration.

Various other objects and advantages will appear from the followingdescription of several embodiments of the invention, and the novelfeatures will be particularly pointed out hereinafter in connection withthe appended claims.

The present invention provides a circuit capable of producing from areceived unipolar binary signal having considerable noise and otherunwanted spurious amplitude variations, a new and correspondinglyinverted binary output signal possessing none of the undesiredcharacteristics. In doing so, the invention improves the switching speedof the received signal, as well as reestablishing a pair of binaryvoltage level standards for use in the following portions of the system.

The following drawings accompany this description:

FIGURE 1 is a circuit schematic of a preferred configuration of theinvention.

FIGURE 2 is a composite characteristic curve imposed on an idealizedcurrent/voltage characteristic curve of a typical tunnel diode for thefull circuit operation cycle.

FIGURES 3A and 3B are composite characteristic curves of the tunneldiode and transistor circuit with their respective circuits shown on theright hand side of their corresponding waveforms.

FIGURES 4A and 4B illustrate dynamic signal waveforms into and out ofthe circuit of FIGURE l.

FIGURES 5A and 5B also illustrate dynamic signal waveforms of the FIGURE1 circuit but the signals have higher repetition rates than those ofFIGURES 4A and 4B.

FIGURE 6A is a schematic diagram of another embodiment, employing theinventive device.

FIGURE 6B illustrates the response waveforms taken of the circuit shownon schematic 6A.

FIGURES 7A and 7B are current/ voltage characteristic curves ofquiescent and trigger actuated states of the schematic diagram of FIGURE6A.

FIGURE 8 is a logical representation of possible circuit organizationenabled by said inventive device.

Referring now in particular to FIGURE 1, the binary signal voltageinverter and standardizer is shown being operated from an emitterfollower input gate. The standardizer section of the figureschematically illustrates the transistor 1-10 connected in the commonemitter fashion having its emitter e returned to a positive source ofvoltage +V The collector c of the transistor 1-10 is returned to anegative source of voltage V through the resistor 1-16. The resistor1-14 is connected between the collector c and the base 11 of thetransistor. The tunnel diode 1-12 is connected across and poled in thesame direction as the emitter e-to-base b junction of the transistorl-lt). The base b of the transistor 1-10 is also connected to receive abinary input signal E from the emitter follower input gate transistorl-Zfl. The higher positive level and the lower positive level of thebinary signal are referred to as E and E respectively. The collector cof the transistor 1-20 is returned to a negative voltage --V which isequal to, but in the opposite direction of, the positive voltage +V towhich the emitter of transistor 1-10 is returned. The base 11 of thetransistor 1-20 is the input terminal to receive the binary input signalto be applied to the voltage inverter and standardizer. The emitter e ofthe transistor 1-20 is returned to a positive voltage source +V which isequal to, but of the opposite polarity of, V,,, through a seriallyconnected pair of resistors 1-18, 1-21. The base b of the transistor1-10 is connected to the junction of the serially connected resistors1-18 and 1-21. The transistor 1-20, when the schematic of FIGURE 1 isoperative, receives a plurality of binary signals, each through a diode.

The operation of this diode input gate is not the normally expectedoperation of gates associated with logical gate junctures in a digitalcomputer. The present invention utilizes the input gate transistor inits active region continuously. Thus, the transistor 1-20 is operatedentirely and continuously in its active region. It is never in itscutoff or its saturated condition. The operation of the transistoremitter follower and its input gates in this fashion has inherentdisadvantages. In fact, it is these disadvantages which without thepresent invention have resulted in its rejection in prior systems. Theprime disadvantage is the susceptibility of the gates to erroneousactivation by noise or spurious signals.

The basic gate shown in FIGURE 8 is a diode-AND, transistor-ORconfiguration, evolved from the hybrid transistor-diode logic technique,with the OR performed at the common-emitter node of emitter-followersfed by each AND gate of the functional block. The circuit is anonsaturating, non cutofl, emitter-follower, and thus takes fulladvantage of the gain-bandwidth capability of the transistor. For anystatic combination of signals, a lowimpedance path exists from thecontrolling inputs to the output set up by the inputs. The importance ofthis path can be appreciated by noting that there is no referencethreshold for any node to clamp on, so that current fiows in all of thecontrolling diodes, and in the output emitterfollower. The only diodescut off are those receiving signals which are in opposition to thesignals currently holding the output level. Thus, input changes areadmitted d rectly to the gating nodes, without the necessity forovercoming a back-biased switch, and speed is enhanced. Since thistechnique provides little noise immunity in the gate,

standardizing circuits with good noise immunity were required betweencascades of limited length. The present invention was devised to satisfythis requirement. Instability of the emitter-followers must also beconsidered, but this problem reduces basically to a layout and packagingburden, with means made available for local suppression of oscillationswhere they cannot be eliminated by design.

In the configuration shown in FIGURE 8, the emitterfollower currentsource is split among the input sources of the driven gates and thesmall standby source at the emitter itself. Each input source is capableof charging the expected stray and wiring capacitance and the nodecapacitances of its own gate Within a nanosecond response limit, in theevent that a rapid rise at the base cuts off the emitter-follower. Thebase-node current source must be capable of discharging the emitter nodewith the minimum-B (beta) transistor, in the event that diodes are cutoff by a rapid negative transition.

The diode forward voltage drop and the transistor emitter-to-basevoltage must be matched as nearly as is economically feasible over theextents of their operating ranges. Therefore, diode drops over aconduction range between 1 ma. (milliamp) and 3 ma. must be of the sameorder of magnitude as emitter-junction drops over an emitter-currentrange of 7 ma. to 20 ma. High-speed germanium diodes have been found tofit the requirement reasonably well in conjunction with highgain-bandwidth germanium transistors of the 2N964 class, yieldingattenuation on the order of 50 mv. per stage, requiring standardizationafter ten ANDOR stages.

The need previously mentioned for a high-speed, noise immune voltagestandardizer would be, ideally, a bistable circuit having low gainexcept during the transient regenerative switching period.

To meet this demand, the present inventive circuit shown in FIGURE 3Bwas developed. In FIGURE 3A, the basic principle governing bistableoperation of a transistor by a tunnel diode is illustrated. The tunneldiode load line is a composite of the negative current source and theemitter junction in parallel, and two stable operating points arepossible, one with the emitter at nearly zero bias and the other with asmuch forward bias as is necessary to turn the transistor on. Switchingcan be accomplished by varying the bias load line slope or intercept.This is done by connecting a signal current source into the base node.The impedance of this source must be sufficiently low that the minimumpossible signal is capable of unaided switching of the tunnel diode.

In the inventive circuit shown in FIGURE 3B, the bias is made to dependupon both the input and output states of an inverter. If the resistors R(3-18) and R (3-14) are assumed equal, for the sake of simplicity, theeffective bias source is a resistance of one-half the R +R value,returned to a source voltage halfway between the input and output (E Eterminal voltages of the inverter. When the input and output voltagesare at opposite extremes, the load line is centered in a bistableposition, and the circuit is stable in the condition to which it waslast switched. The presence of the resistor R (3-14) connected between band c of transistor 3-10 makes it possible to switch the bistablecircuit either up or down with a simple level change at the input,without need for either bipolar signals or separate resetting pulses.

If the initial voltage level at the input is low E and the output high Ethe tunnel diode 3-12 is in its highvoltage state, and the transistor3-10 is on. Then, when the input voltage E rises, with the outputvoltage already high E the tunnel diode current falls below its valleypoint, and the tunnel diode 3-12 switches to the low voltage state,switching the transistor 3-10 off. The output voltage then falls E andreturns the circuit to a quiescent condition. Although the circuit inthis condition permits a high current through the tunnel diode due tothe voltage which is low at the collector of transistor 3-10 it isunderstood that the magnitude of current is insufficient to cause thetunnel diode to exceed its pea-k.

Finally, when the input signal voltage falls again E with the lowvoltage output E the combined current ib and ia drawn through the inputresistor 3-18 and resistor 3-14 exceeds the peak current of the tunneldiode 3-12, switching it to its high voltage state and turning thetransistor 3-10 back on.

The noise rejection of such an inverter is better than one-half theminimum switching signal swing because of the hysteresis effectcontributed by the switching of the tunnel diode. For maximum responsespeed, as previously discussed, the transistor circuit is designed tooperate nonsaturating and non-cutolf.

The final version of the circuit is illustrated in FIGURE 1. The inputlevels E and E represent the minimum swing expected after attenuationand shift of the output level through a cascade of logic as long as tenstages. The shift is positive through the gates described previously, sothat the upper limit E is always exceeded in practice. The lower limit Eallows a shift of about 1.8 v. from the output of one standardizercircuit to the input of the next one located ten logic stages later. Thefirst stage of logic, as illustrated in FIGURE 8, shifts the lower levelto about +0.2. v., because of the clamping action imposed by theconnection to ground of the collectors of emitterfollower transistors QQ Q Then, to pass through nine more stages, such as is shown in FIGURE8, with less than 0.8 v. of shift, the shift per stage need only be lessthan mv. (millivolts). This requirement can be easily met by thetransistor-OR gate of FIGURE 8.

The signal traces of FIGURES 4A and 4B show the response of a model ofthe circuit to an input swing, FIG- URE 4A, of 0 to +1.8 v. The invertedoutput of FIG. 4B swings from -0.9 to +1.8 v. The waveform of FIG. 4Ashows a negative-going input pulse at a relatively low repetition rateproducing the output positive-going waveform of FIG. 4B. The FIGURES 5Aand 5B show a positive-going input pulse (FIG. 5A) at a higherrepetition rate producing a negative-going output pulse (FIG. 5B). Theidentical characteristics of corresponding edges of the FIGS. 4A and 5Aand of FIGS. 4B and 5B indicate that the circuit is dependable from DC.up to at least a 40-mc. switching rate. (The time scale is 10 ns. percentimeter.) The circuit delay between FIGS. 4A and 4B and FIGS. 5A and5B is about 3 ns. in response to an input rise, and 4 ns. at the fall.The output rise and fall times are on the order of 5 ns., without aload. An output emitter-follower can maintain this rise time under loadat the expense of an additional delay of 1 or 2 ns.

The second embodiment, a clocked, single-output, single-input flip-flopcircuit shown in FIG. 6A has also been derived from this circuit. Itswaveforms are shown in FIGURE 6B. The input resistors form two parallelbranches, one branch resistor 6-10 receiving signal information, theother resistor 6-12 carrying a bias which provides bistable operation,with a bipolar clock pulse ET superimposed. The signal resistor 6-10 andidle current resistor 6-14 branches are designed to provide so littlecurrent that they do not disturb the bistable bias between clock pulses.The clock amplitude is insufi'icient to exceed the tunnel-diode 6-18switching points of FIGURE 7B if the input E and output E of the circuitare at opposite levels. However, if the input and output are both high Eand E they reinforce the positive clock swing suflishould change. Acomplementary output can be provided, if necessary, by adding theinverter described previously.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to the preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in the artwithout departing from the spirit of the invention. It is the intention,therefore, to be limited only as indicated by the scope of the followingclaims.

What is claimed is:

1. A binary signal level standardizer comprising: a pair of seriallyconnected resistors having a single common connection junction point anda first and a second end terminal, a power source connected to saidfirst end terminal, a tunnel diode connected to said second endterminal, said tunnel diode to be normally conducting through said pairof serially connected resistors in a first voltage mode, a single sourceof binary pulses to provide a train of pulses each having a leading anda trailing edge, a further resistor connected between said single sourceof binary signal pulses and said second end terminal of said pair ofserially connected resistors, a transistor having an emitter, a base,and a collector electrode, said base electrode also connected to saidsecond end terminal, said collector electrode connected to the singlecommon connection junction point between said pair of serially connectedresistors, said further resistor and the resistor connected between thebase and collector electrodes having substantially equal resistancevalues, said emitter electrode connected to a reference potential, saidtunnel diode being activated to a second voltage mode upon receipt ofthe leading edge of each pulse in said train of pulses from said binarysource to cause said transistor to be responsively switched by saidchange in voltage mode of said tunnel diode and said tunnel diode beingactively returned to its first voltage mode upon receipt of the trailingedge of each pulse to provide a standardizer capable of binaryactivation solely dependent upon the train of input pulses from saidsingle source.

2. A binary signal voltage level standardizer and inverter circuithaving a first and a second stable state comprising a unipolar squarewave input voltage source, a transistor having an emitter, a base, and acollector electrode, an output resistor connected between a fixedvoltage source and said collector electrode, a reference voltage sourceconnected to said emitter electrode, a common terminal junction, atunnel diode oriented in the same poled direction as the transistoremitter and base electrodes and having two tunnel diode electrodes withone connected to said emitter electrode and the other to said junction,a single unbypassed feedback resistor connected between said collectorelectrode and said junction, a direct connection from said junction tosaid base electrode, and an input resistor having a resistance valuesubstantially equal to the resistance of said feedback resistor andhaving two terminals with one terminal connected to said junction andthe other terminal directly connected to said unipolar square wave inputvoltage source to enable each successive voltage level change of each ofthe square wave pulses to cause the said circuit to switch from one ofits two stable states to its other stable state.

3. A circuit as recited in claim 2 wherein said source of square wavepulses is comprised of an emitter follower transistor circuit in whichsaid input resistor comprises a load resistor for said emitter followercircuit and including an emitter source of supply voltage for saidemitter follower circuit of a polarity of reverse bias with respect tothe poled direction of said tunnel diode orientation.

References Cited UNITED STATES PATENTS 3,171,979 3/1965 Corsiglia30788.5 3,185,864 5/1965 Amodei 30788.5 3,218,466 11/1965 Walsh et al.30788.5

OTHER REFERENCES GE Tunnel Diode Manual, first edition, 1961, pp. 48-49.

JOHN S. HEYMAN, Primary Examiner.

ARTHUR GAUSS, Examiner.

J. ZAZWORSKY, Assistant Examiner.

1. A BINARY SIGNAL LEVEL STANDARDIZER COMPRISING: A PAIR OF SERIALLYCONNECTED RESISTORS HAVING A SINGLE COMMON CONNECTION JUNCTION POINT ANDA FIRST AND A SECOND END TERMINAL, A POWER SOURCE CONNECTED TO SAIDFIRST END TERMINAL, A TUNNEL DIODE CONNECTED TO SAID SECOND ENDTERMINAL, SAID TUNNEL DIODE TO BE NORMALLY CONDUCTING THROUGH SAID PAIROF SERIALLY CONNECTED RESISTORS IN A FIRST VOLTAGE MODE, A SINGLE SOURCEOF BINARY PULSES TO PROVIDE A TRAIN OF PULSES EACH HAVING A LEADING ANDA TRAILING EDGE, A FURTHER RESISTOR CONNECTED BETWEEN SAID SINGLE SOURCEOF BINARY SIGNAL PULSES AND SAID SECOND END TERMINAL OF SAID PAIR OFSERIALLY CONNECTED RESISTORS, A TRANSISTOR HAVING AN EMITTER, A BASE,AND A COLLECTOR ELECTRODE, SAID BASE ELECTRODE ALSO CONNECTED TO SAIDSECOND END TERMINAL, SAID COLLECTOR ELECTRODE CONNECTED TO THE SINGLECOMMON CONNECTION JUNCTION POINT BETWEEN SAID PAIR OF SERIALLY CONNECTEDRESISTORS, SAID FURTHER RESISTOR AND THE RESISTOR CONNECTED BETWEEN THEBASE AND COLLECTOR ELECTRODES HAVING SUBSTANTIALLY EQUAL RESISTANCEVALUES, SAID EMITTER ELECTRODE CONNECTED TO A REFERENCE POTENTIAL, SAIDTUNNEL DIODE BEING ACTIVATED TO A SECOND VOLTAGE MODE UPON RECEIPT OFTHE LEADING EDGE OF EACH PULSE IN SAID TRAIN OF PULSES FROM SAID BINARYSOURCE TO CAUSE SAID TRANSISTOR TO BE RESPONSIVELY SWITCHED BY SAIDCHANGE IN VOLTAGE MODE OF SAID TUNNEL DIODE AND SAID TUNNEL DIODE BEINGACTIVELY RETURNED TO ITS FIRST VOLTAGE MODE UPON RECEIPT OF THE TRAILINGEDGE OF EACH PULSE TO PROVIDE A STANDARDIZER CAPABLE OF BINARYACTIVATION SOLELY DEPENDENT UPON THE TRAIN OF INPUT PULSES FROM SAIDSINGLE SOURCE.